Design and Simulation of FIR Filter using Multiple Constant Multiplication

Abstract

Finite impulse response (FIR) digital filters have potential for high-speed and low-power realization through parallel processing. In this paper, we suggest an efficient implementation of FIR filters using Pipelined Multiple Constant Multiplication (PMCM) technique. MCM methods are widely used for reducing computational complexity of FIR filters. The concept of pipelining has been incorporated that results in reducing the delay of the FIR filter, thereby enhancing the speed and reducing the power dissipation as compared to the non-pipelined techniques. The speed of the multipliers can be increased by reducing the number of partial products. Parallel multipliers are fastest among all multipliers. Booth multiplier is one of the parallel multiplier that operate on signed operands in two’s complement form and have high performance, low power consumption Experimentation on block filters for 16 bits of different block lengths indicates that, compared to sample-by-sample MCM based FIR Filters. The simulation of this design is done by using Modelsim 6.2c. The design synthesis and power analysis are carried out using Xilinx ISE 12.1v.

Keywords

Finite impulse response; Multiple Constant Multiplication; Booth’s Muliplier; Filters

References

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